The present invention relates to a dynamic RAM. More specifically, the invention relates to a dynamic RAM employing a dual word line system including a word driver sequence and a sense amplifier sequence for respective of a plurality of separated blocks.
In general, a dynamic RAM includes a memory cell array for outputting holding data to a bit line when selected and sense amplifiers for amplifying the outputs. Typical construction of the dynamic RAM will be discussed with reference to FIGS. 4 and 5.
In FIG. 4, memory cells 10 and 14 are provided at both sides of a sense amplifier 12. Transfer gates TG are provided corresponding to respective memory cells. Each transfer gate TG has a function to block and establish electrical connection between the corresponding memory cell and the sense amplifier 12.
A construction, in which the transfer gate TG is arranged in distributing manner, is illustrated in FIG. 5. In FIG. 5, the cell arrays 10A, 10B, . . . 10N and word driver sequences 11A, 11B, . . . 11N are arranged alternately. The sense amplifier sequences 12A, 12B, . . . 12N are provided corresponding to respective cell arrays. On each portion where the word driver sequence and the sense amplifier are intersect, a transfer data driver circuit (hereafter referred to as TG driver circuit) 13A, 13B, . . . 13N are provided. For driving these TG driver circuits, a main TG driver circuit 130 is provided. It should be noted that a decoding output of a word decoder 110 is transmitted through a main word line MW for selecting desired word driver (e.g. the driver 111 shown by hatched portion) among the word driver sequences. By this, a sub-word line SW is activated to select desired one of the memory cell in the cell array.
When the memory cell is selected, the transfer gate corresponding to the selected cell must be placed at a state for establishing the electrical connection, and the transfer gate corresponding to the non-selected cell must be placed at a state for blocking electrical connection. Therefore, the main TG driver circuit 130 feeds a main transfer gate signal. By this, the TG driver circuit feeds a sub-transfer gate signal to selectively placing the transfer gate into the state for establishing or blocking electrical connection.
For example, when the word driver 111 is selected as shown, a main transfer gate signal MTG0 is output from the main TG driver circuit 130. Then, a sub-transfer gate signal STG00 is output from the TG driver circuit 13C. Then, the selected memory cell is connected to the sense amplifier. On the other hand, the non-selected memory cell provided at the opposite side (not shown) of the cell array 10C across the memory cell is electrically disconnected from the sense amplifier.
Namely, referring again to FIG. 4, the memory cells 10 and 14 are provided at both sides of the sense amplifier 12. The transfer gates TG corresponding to respective memory cells 12 are controlled by the sub-transfer gate (sub-TG) signal STG00, STG01. By the sub-TG signals STG00 and STG01, one of the memory cells 10 and 14 is electrically connected to the sense amplifier 12 and the other is electrically disconnected to the sense amplifier so that the selected memory cell is accessed.
Here, when the transfer gate TG is formed of nMOS transistor (hereafter referred to as nMOSTr), a high potential level of the control signal must be elevated potential VPP (higher than the power source voltage VCC) in order to completely transmit the high potential of the sense amplifier 12 to the memory cells. Therefore, in the dynamic RAM employing dual word line system, when the intersections of word driver sequences and sense amplifier sequences, the TG driver circuit is constructed as shown in FIG. 6.
Namely, the TG driver circuit 130 comprises a pMOS transistor (hereafter referred to as pMOSTr) Q15 for transmitting the elevated potential VPP and nMOSTr Q11 for transmitting a grounding potential GND (GND level). Then, When the main transfer gate (main TG) signal MTG0 is at the elevated potential VPP, nMOSTr Q11 turns ON. Then, the sub-TG signal STG00 becomes the GND level. On the other hand, when the signal MTG0 is GND level, nMOSTr Q11 turns ON. Then, the sub-TG signal STG00P becomes the elevated potential VPP. The TG driver circuit for outputting the TG signal STG01 comprises pMOSTr Q16 and nMOSTr Q12 in similar manner to the circuit 13C and is controlled by a main TG signal MTG1.
The operation of the TG driver circuit constructed as set forth above will be discussed with reference to FIG. 7. At the stand-by state, the transfer gate signals MTG0 and MTG1 are initially at GND level. At this time, the sub-TG signals STG00 and STG01 are both held at the elevated potential VPP. Namely, in FIG. 4, the memory cell side and the sense amplifier side of the bit line are connected (period 1 in FIG. 7). When the sense amplifier is selected, the main TG signal of the selected side, e.g. MTG0 is held at the GND level, while the main TG signal, e.g. MTG1, of the non-selected side is risen to the VPP level (period 2 of FIG. 7). Then, only the sub-TG signal STG01 of the non-selected side is lowered down to the GND level so that the memory cell side and the sense amplifier side of the bit line is electrically disconnected.
Upon termination of the operation of the sense amplifier, the main TG signal MTG1 of the non-selected side is lowered down to the GND level to rise the sub-TG signal STG01 to the VPP level. Thus, the both sides of the sense amplifier is connected to the memory cells to be placed into the stand-by state (period 3 of FIG. 7).
In the conventional dynamic RAM constructed as set forth above, since the TG driver circuit for separating the bit line between the memory cell side and the sense amplifier side upon the operation of the sense amplifier employs a circuit using the elevated potential VPP, semiconductor well has to be provided separately from the sense amplifier in the semiconductor substrate. This will be further discussed with reference to FIG. 8.
FIG. 8 is a section showing a semiconductor well structure of the conventional dynamic RAM. As set forth above, since TG driver circuit employs pMOSTr using VPP as power source, it becomes necessary to provide N-well 100 of VPP level. Also, nMOSTr forming the sense amplifier normally draw a substrate voltage to a negative voltage VSUB similarly to the memory cell transistor, P-wells 101 and 102 of VSUB become necessary. Furthermore, in order to separate the P-wells from the substrate, N-wells 103 and 104 of VCC level become necessary. In addition, since the N-well 100 of the TG driver circuit and N-wells 103 and 104 of the sense amplifier have different potential, P-wells 105 and 106 of the GND level become necessary. For the reason set forth above, the well structures of the TG driver circuit and the sense amplifier become as illustrated in FIG. 8.
It should be appreciated that 201 and 202 are N-wells of VCC level forming a peripheral circuit, and 203 and 204 are P-wells of GND level.
Accordingly, when the TG driver circuits are arranged in distributing manner, chip area is increased to cause rising of the cost therefor.
On the other hand, in the above-mentioned conventional dynamic RAM, since the sub-TG signals are held at the elevated potential even at the stand-by state, power consumption is relatively large.